library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity PC is
    port(Clk,LD_PC: in  bit;
         PCMUX_out: in  unsigned(15 downto 0);
         PCval:     out unsigned(15 downto 0));
    end entity PC;
    
architecture build of PC is
    begin
        process(LD_PC,PCMUX_out,Clk)
            begin
                if Clk = '1' and Clk'event then
                    if LD_PC = '1' then
                        PCval <= PCMUX_out;
                    end if;                    
                end if;
            end process;
    end build;